Logic compatible RRAM structure and process
US9537094B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 30, 2015 |
| Grant date | Jan 3, 2017 |
| Priority date | — |
| Expiry date | Dec 30, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8833
Abstract
A memory cell and method including a first electrode formed through a first opening in a first dielectric layer, a resistive layer formed on the first electrode, a spacing layer formed on the resistive layer, a second electrode formed on the resistive layer, and a second dielectric layer formed on the second electrode, the second dielectric layer including a second opening. The first dielectric layer formed on a substrate including a first metal layer. The first electrode and the resistive layer collectively include a first lip region that extends a first distance beyond the first opening. The second electrode and the second dielectric layer collectively include a second lip region that extends a second distance beyond the first opening. The spacing layer extends from the second distance to the first distance. The second electrode is coupled to a second metal layer using a via that extends through the second opening.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.