Warpage control in the packaging of integrated circuits
US9538582B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 26, 2012 |
| Grant date | Jan 3, 2017 |
| Priority date | — |
| Expiry date | Oct 28, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/37001
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method includes placing a first package component over a vacuum boat, wherein the vacuum boat comprises a hole, and wherein the first package component covers the hole. A second package component is placed over the first package component, wherein solder regions are disposed between the first and the second package components. The hole is vacuumed, wherein the first package component is pressed by a pressure against the vacuum boat, and wherein the pressure is generated by a vacuum in the hole. When the vacuum in the hole is maintained, the solder regions are reflowed to bond the second package component to the first package component.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.