L2 flush and memory fabric teardown
US9541984B2 · kind B2 · utility
9Cited by
1References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 5, 2013 |
| Grant date | Jan 10, 2017 |
| Priority date | — |
| Expiry date | Dec 18, 2033 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and a method which include one or more processors, a memory coupled to at least one of the processors, a communication link coupled to the memory, and a power management unit. The power management unit may be configured to detect an inactive state of at least one of the processors. The power management unit may be configured to disable the communication link at a time after the processor enters the inactive state, and disable the memory at another time after the processor enters the inactive state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.