Method and apparatus for camouflaging a standard cell based integrated circuit with micro circuits and post processing
US9542520B2 · kind B2 · utility
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34Claims
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Key dates
| Filing date | Jul 12, 2013 |
| Grant date | Jan 10, 2017 |
| Priority date | — |
| Expiry date | May 21, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for camouflaging an application specific integrated circuit (ASIC), wherein the ASIC comprises a plurality of interconnected functional logic is disclosed. The method adds functionally inert elements to the logical description or provides alternative definitions of standard logical cells to make it difficult for reverse engineering programs to be used to discover the circuit's function. Additionally, post processing may be performed on GDS layers to provide a realistic fill of the empty space so as to resemble structural elements found in a functional circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.