System and method for improving memory performance and identifying weak bits
US9543044B2 · kind B2 · utility
4Cited by
10References
28Claims
0Family size
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Key dates
| Filing date | Nov 7, 2013 |
| Grant date | Jan 10, 2017 |
| Priority date | — |
| Expiry date | Jan 8, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/52
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to an embodiment described herein, a method for testing a memory includes receiving an address and a start signal at a memory, and generating a first detector pulse at a test circuit in response to the start signal. The first detector pulse has a leading edge and a trailing edge. A data transition of a bit associated with the address is detected. The bit is a functional bit. The method further includes determining whether the bit is a weak bit by determining whether the data transition occurred after the trailing edge.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.