Patent · US Active

System-level packaging methods and structures

US9543269B2 · kind B2 · utility

0Cited by

9References

12Claims

0Family size

Assignee

NANTONG FUJITSU MICROELECTRONICS CO., LTD. · CN

Inventors

Yujuan Tao · Nantong, CN
Lei Shi · Shanghai, CN
Honghui Wang · Beijing, CN

Key dates

Filing date	Mar 22, 2012
Grant date	Jan 10, 2017
Priority date	—
Expiry date	Mar 22, 2032

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/15311
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A system-level packaging method includes providing a packaging substrate having a first functional surface and a second surface with wiring arrangement within the packaging substrate and between the first functional surface and the second surface. The method also includes forming at least two package layers on the first functional surface of the packaging substrate, wherein each package layer is formed by subsequently forming a mounting layer, a sealant layer, and a wiring layer. Further, the method includes forming a top sealant layer and planting connection balls on the second functional surface of the packaging substrate.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.