Production of spacers at flanks of a transistor gate
US9543409B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Sep 16, 2015 |
| Grant date | Jan 10, 2017 |
| Priority date | — |
| Expiry date | Sep 16, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/685
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The production of spacers at flanks of a transistor gate, including a step of forming a dielectric layer covering the gate and a peripheral region of a layer of semiconductor material surrounding the gate, including forming a superficial layer covering the gate and the peripheral region; partially removing the superficial layer configured so as to completely remove the superficial layer at the peripheral region while preserving a residual part of the superficial layer at the flanks; and selective etching of the dielectric layer vis-à-vis the material of the residual part of the superficial layer and vis-à-vis the semiconductor material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.