Asymmetric multi-gate finFET
US9543435B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 20, 2015 |
| Grant date | Jan 10, 2017 |
| Priority date | — |
| Expiry date | Oct 20, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/021
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An asymmetrical finFET device includes at least one semiconductor fin on an upper surface of a semiconductor substrate. The fin extends along a length of the semiconductor substrate to define a fin length. A plurality of gate structures wrap around the sidewalls and upper fin surface of the fin. The plurality of gate structures includes at least one desired gate structure surrounded by at least one sacrificial gate structure. A first source/drain region is formed adjacent a first sidewall of the at least one desired gate structure, and a second source/drain region is formed adjacent a second sidewall of the at least one desired gate structure opposite the first sidewall. The dimensions of the first and second source/drain regions are asymmetrical with respect to one another.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.