Patent · US Active

Integrated circuit with dual stress liner boundary

US9543437B2 · kind B2 · utility

1Cited by
7References
7Claims
0Family size

Assignee

Inventors

Key dates

Filing dateSep 23, 2015
Grant dateJan 10, 2017
Priority date—
Expiry dateSep 23, 2035

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10D89/00

Abstract

An integrated circuit with DSL borders perpendicular to the transistor gates primarily inside the nwell and with DSL borders parallel to the transistor gates primarily outside the nwell. A method for forming an integrated circuit with DSL borders perpendicular to the transistor gates primarily inside the nwell and with DSL borders parallel to the transistor gates primarily outside the nwell.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.