Contact resistance reduction technique
US9543438B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 15, 2014 |
| Grant date | Jan 10, 2017 |
| Priority date | — |
| Expiry date | Oct 15, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An embodiment is a method of manufacturing a semiconductor device, the method including forming a first gate over a substrate, forming a recess in the substrate adjacent the first gate, epitaxially forming a strained material stack in the recess, the strained material stack comprising at least three layers, each of the at least three layers comprising a dopant. The method further includes co-implanting the strained material stack with dopants comprising boron, germanium, indium, tin, or a combination thereof, forming a metal layer on the strained material stack, and annealing the metal layer and the strained material stack forming a metal-silicide layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.