Electrode materials and interface layers to minimize chalcogenide interface resistance

US9543515B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• F. Daniel Gealy · Kuna, US
• Andrea Gotti · Vaprio d'Adda, IT
• Davide Colombo · Rescaldina, IT
• Kuo-Wei Chang · Waltham, US

Key dates

• Filing date: Nov 7, 2013
• Grant date: Jan 10, 2017
• Expiry date: Feb 15, 2034

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10N70/8828

Abstract

A phase-change memory cell having a reduced electrode-chalcogenide interface resistance and a method for making the phase-change memory cell are disclosed: An interface layer is formed between an electrode layer and a chalcogenide layer that and provides a reduced resistance between the chalcogenide-based phase-change memory layer and the electrode layer. Exemplary embodiments provide that the interface layer comprises a tungsten carbide, a molybdenum carbide, a tungsten boride, or a molybdenum boride, or a combination thereof. In one exemplary embodiment, the interface layer comprises a thickness of between about 1 nm and about 10 nm.