Determination of configuration values and configuration of frequency multiplier and frequency divider circuitry
US9543934B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 9, 2015 |
| Grant date | Jan 10, 2017 |
| Priority date | — |
| Expiry date | Aug 5, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In an approach for determining multiplier values and divisor values for programming frequency multiplier and divider circuits in a clock network, respective requested frequency values and respective tolerance levels relative to the requested frequency values for a plurality of clocked circuit blocks are used. Multiple solution sets are generated, with each solution set including a multiplier value and an associated set of values of divisors, such that resulting actual frequencies satisfy the respective tolerance levels. Respective sets of clocked error values are determined for the plurality of solution sets, with each clocked error value corresponding to a clocked circuit block. Solution-set-error values are determined as a function of the respective sets of clocked error values, and the solution set having the least solution-set-error value is selected and stored.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.