Reconfigurable voltage desensitization circuit to emulate system critical paths
US9543936B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 22, 2015 |
| Grant date | Jan 10, 2017 |
| Priority date | — |
| Expiry date | Jun 22, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00071
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit for controlling a clock signal may include a voltage source that provides a bias voltage, and at least one delay element having a non-linear capacitive load coupled to an output of the delay element. The non-linear capacitive load receives the bias from the voltage source and controls a delay magnitude applied to a plurality of pulses of the clock signal by the delay element. Based on the bias having a first scaled voltage, the delay magnitude that is applied to the plurality of clock pulses is increased in order to generate a frequency correction to the operating frequency of a microprocessor based on a variation to a microprocessor supply voltage. Based on the bias having a second scaled voltage, the delay magnitude that is applied to the clock pulses is maintained to retain the operating frequency of the clock during the variation to the supply voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.