Multiplexer-memory cell circuit, layout thereof and method of manufacturing same
US9543958B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 3, 2016 |
| Grant date | Jan 10, 2017 |
| Priority date | — |
| Expiry date | Feb 3, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1776
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated circuit includes a plurality of logic tiles, wherein each logic tile includes a plurality of edges and, is configurable to communicate, during operation, with at least one adjacent logic tile, and wherein a first logic tile includes: (i) a plurality of static memory cells to store data, wherein each memory cell includes a first output, (ii) a multiplexer including inputs, an output and input selects, (iii) a plurality of poly-silicon conductors, each poly-silicon conductor is disposed in the substrate and connected to the first output of an associated memory cell, (iv) poly-silicon extensions, each poly-silicon extension is (a) connected to an associated poly-silicon conductor and (b) coupled to an associated input select of the multiplexer, wherein the poly-silicon extensions are disposed in the substrate and at least partially under a metal conductor in the first logic tile.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.