Pipelining an asynchronous memory reusing a sense amp and an output latch
US9548089B2 · kind B2 · utility
1Cited by
6References
19Claims
0Family size
Assignee
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Key dates
| Filing date | Jun 18, 2015 |
| Grant date | Jan 17, 2017 |
| Priority date | — |
| Expiry date | Jun 18, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1066
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An asynchronous memory includes a memory array, a sense amplifier, an output latch, and a controller. In response to a clock signal from an external circuit requesting a read operation, the controller provides the clock signal to the memory array to read data, and controls the sense amplifier and the output latch to provide the functionality of a flip-flop master and slave so that the read operation delay through the output latch to the external circuit is removed from a first read cycle of two sequential read cycles.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.