Patent · US Active

Method including a formation of a control gate of a nonvolatile memory cell and semiconductor structure including a nonvolatile memory cell

US9548312B1 · kind B1 · utility

12Cited by
4References
11Claims
0Family size

Assignee

Inventors

Key dates

Filing dateNov 10, 2015
Grant dateJan 17, 2017
Priority date
Expiry dateNov 10, 2035

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10D64/035

Abstract

A method includes providing a semiconductor structure including a nonvolatile memory cell element and one or more electrically insulating layers covering the nonvolatile memory cell element. The nonvolatile memory cell element includes a source region, a channel region, a drain region and a floating gate over at least a first portion of the channel region. A first opening is formed in the electrically insulating layers over the floating gate, a control gate insulation layer is deposited, and a second opening is formed in the electrically insulating layers over the drain region. The first opening and the second opening are filled with an electrically conductive material. The electrically conductive material in the first opening provides a control gate of the nonvolatile memory cell element and the electrically conductive material in the second opening provides an electrical contact to the drain region.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.