Cut mask design layers to provide compact cell height
US9551923B2 · kind B2 · utility
10Cited by
0References
19Claims
0Family size
Assignee
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Key dates
| Filing date | Apr 8, 2014 |
| Grant date | Jan 24, 2017 |
| Priority date | — |
| Expiry date | Dec 26, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/974
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
Some embodiments relate to a method of designing an integrated circuit layout. In this method, a plurality of design shapes are provided on different design layers over an active area within a graphical representation of the layout. A connection extends perpendicularly between a first design shape formed on a first design layer and a second design shape formed on the first design layer. First and second cut mask shapes on first and second cut mask design layers, respectively, are generated. The first cut shape removes portions of the first design layer and the second cut shape removes portions of the second design layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.