Schedulers with load-store queue awareness
US9552196B2 · kind B2 · utility
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4Claims
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Key dates
| Filing date | Jun 19, 2015 |
| Grant date | Jan 24, 2017 |
| Priority date | — |
| Expiry date | Jun 19, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3854
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a computer-implemented method includes tracking a size of a load-store queue (LSQ) during compile time of a program. The size of the LSQ is time-varying and indicates how many memory access instructions of the program are on the LSQ. The method further includes scheduling, by a computer processor, a plurality of memory access instructions of the program based on the size of the LSQ.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.