Method and apparatus related to cache memory
US9552301B2 · kind B2 · utility
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2References
17Claims
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Key dates
| Filing date | Jul 15, 2013 |
| Grant date | Jan 24, 2017 |
| Priority date | — |
| Expiry date | Dec 24, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/126
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache includes a cache array and a cache controller. The cache array has a plurality of entries. The cache controller is coupled to the cache array. The cache controller evicts entries from the cache array according to a cache replacement policy. The cache controller evicts a first cache line from the cache array by generating a writeback request for modified data from the first cache line, and subsequently generates a writeback request for modified data from a second cache line if the second cache line is about to satisfy the cache replacement policy and stores data from a common locality as the first cache line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.