High-speed peripheral component interconnect (PCIe) input-output devices with receive buffer management circuitry
US9552323B1 · kind B1 · utility
7Cited by
4References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 5, 2013 |
| Grant date | Jan 24, 2017 |
| Priority date | — |
| Expiry date | Mar 16, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/0026
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Interface circuitry is provided to control the flow of data transmitted over a high-speed serial link. The interface circuitry may receive data over a high-speed serial link and store the received data in a receive buffer. The receive buffer may be connected to an additional buffer in an application layer module. The application layer module may produce credits based on the processing capacity of the additional buffer and send those credits to the interface circuitry. The interface circuitry may then send these credits over the high speed link.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.