Integrated circuit with power network aware metal fill
US9552453B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 22, 2015 |
| Grant date | Jan 24, 2017 |
| Priority date | — |
| Expiry date | Sep 22, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In the physical design of an integrated circuit, comparing metal fill locations with an average least resistance path (LRP) for a cell and then filling the location with either power or ground tiles based on the comparison. For each metal layer, all of the metal fill locations are determined and nearby metal fills, i.e., those within a predetermined radius of a located metal fill are connected. A Design Rule Check (DRC) is performed to ensure that connected metal fills meet design specifications, for example, that connected metal fills are not too close to a signal line. The metal fill method improves the power integrity of the design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.