Patent · US Active

Semiconductor structure with TRL and handle wafer cavities

US9553013B2 · kind B2 · utility

1Cited by
35References
12Claims
0Family size

Assignee

Inventors

Key dates

Filing dateFeb 26, 2015
Grant dateJan 24, 2017
Priority date—
Expiry dateFeb 26, 2035

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH01L2924/1461
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

A method is disclosed. The method comprises fabricating a device layer on a top portion of a semiconductor wafer that comprises a substrate. The device layer comprises an active device. The method also comprises forming a trap rich layer at a top portion of a handle wafer. The forming comprises etching the top portion of the handle wafer to form a structure in the top portion of the handle wafer that configures the trap rich layer. The method also comprises bonding a top surface of the handle wafer to a top surface of the semiconductor wafer. The method also comprises removing a bottom substrate portion of the semiconductor wafer.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.