Semiconductor device models including re-usable sub-structures
US9553033B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 12, 2015 |
| Grant date | Jan 24, 2017 |
| Priority date | — |
| Expiry date | Jan 12, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/12
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods and tools for generating measurement models of complex device structures based on re-useable, parametric models are presented. Metrology systems employing these models are configured to measure structural and material characteristics associated with different semiconductor fabrication processes. The re-useable, parametric sub-structure model is fully defined by a set of independent parameters entered by a user of the model building tool. All other variables associated with the model shape and internal constraints among constituent geometric elements are pre-defined within the model. In some embodiments, one or more re-useable, parametric models are integrated into a measurement model of a complex semiconductor device. In another aspect, a model building tool generates a re-useable, parametric sub-structure model based on input from a user. The resulting models can be exported to a file that can be used by others and may include security features to control the sharing of sensitive intellectual property with particular users.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.