FET device having a vertical channel in a 2D material layer
US9553199B2 · kind B2 · utility
13Cited by
1References
20Claims
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Key dates
| Filing date | Dec 30, 2014 |
| Grant date | Jan 24, 2017 |
| Priority date | — |
| Expiry date | Dec 30, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/292
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Semiconductor devices and methods of forming the same are provided. A source/drain electrode stack is formed over a substrate, wherein the source/drain electrode stack comprises a first source/drain electrode and a second source/drain electrode. A source/channel/drain layer is formed on a sidewall of the source/drain electrode stack, wherein the source/channel/drain layer comprises a 2D material. A gate stack is formed on the source/channel/drain layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.