Method of integration of a magnetoresistive structure
US9553260B2 · kind B2 · utility
3Cited by
13References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 5, 2015 |
| Grant date | Jan 24, 2017 |
| Priority date | — |
| Expiry date | May 5, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B61/22
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A conductive via disposed beneath a magnetic device and aligned therewith. In certain embodiments, an electrode formed on the conductive via may be polished to eliminate step functions or seams originating at the conductive via from propagating up through the various deposited layers. This integration approach allows for improved scaling of the MRAM devices to, for example, a 45 nanometer node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.