RRAM device with data storage layer having increased height

US9553265B1 · kind B1 · utility

Assignee

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. · TW

Inventors

• Jen-Sheng Yang · Keelung, TW
• Chih-Yang Chang · 員林市, TW
• Chin-Chieh Yang · New Taipei, TW
• Kuo-Chi Tu · Baoshan, TW
• Sheng-Hung Shih · Hsinchu, TW
• Wen-Ting Chu
• Yu-Wen Liao · New Taipei, TW
• Manish Singh · Tracy, US

Key dates

• Filing date: Jan 14, 2016
• Grant date: Jan 24, 2017
• Expiry date: Jan 14, 2036

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B63/30

Abstract

The present disclosure relates to an integrated circuit, which includes a semiconductor substrate and an interconnect structure disposed over the semiconductor substrate. The interconnect structure includes a lower metal layer, an intermediate metal layer disposed over the lower metal layer, and an upper metal layer disposed over the intermediate metal layer. An upper surface of the lower metal layer and a lower surface of the intermediate metal layer are spaced vertically apart by a first distance. A resistive random access memory (RRAM) cell is arranged between the lower metal layer and the upper metal layer. The RRAM cell includes a bottom electrode and a top electrode which are separated by a data storage layer having a variable resistance. The data storage layer vertically spans a second distance that is greater than the first distance.