Network receiver for a network using distributed clock synchronization and a method of adjusting a frequency of an internal clock of the network receiver
US9553716B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 29, 2013 |
| Grant date | Jan 24, 2017 |
| Priority date | — |
| Expiry date | Jun 30, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L12/6418
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A network receiver for a network using distributed clock synchronization and a method of adjusting a frequency of an internal clock of the network receiver are provided. The network receiver receives from the network an input signal and has an internal clock for generating a clock signal. The network receiver further includes a clock bit comparator and an adjustment signal generator. The clock bit comparator compares lengths of a first time period lapsed while receiving at least five consecutive bits of the signal and of an internal clock time interval representing the same number of bits as a number of bits of the first time period. The adjustment signal generator generates a frequency adjustment signal for controlling a frequency of the internal clock in dependence of a result of the comparison of the lengths to reduce a difference between the lengths.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.