Two-level cache locking mechanism

US9558121B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Li-Gao Zei · Braunschweig, DE
• Fernando Latorre · Soria, ES
• Steffen Kosinski · Braunschweig, DE
• Jaroslaw Topp
• Varun K. Mohandru · Braunschweig, DE
• Lutz Naethke · Braunschweig, DE

Key dates

• Filing date: Dec 28, 2012
• Grant date: Jan 31, 2017
• Expiry date: Mar 11, 2034

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F12/1063
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A virtually tagged cache may be configured to index virtual address entries in the cache into lockable sets based on a page offset value. When a memory operation misses on the virtually tagged cache, only the one set of virtual address entries with the same page offset may be locked. Thereafter, this general lock may be released and only an address stored in the physical tag array matching the physical address and a virtual address in the virtual tag array corresponding to the matching address stored in the physical tag array may be locked to reduce the amount and duration of locked addresses. The machine may be stalled only if a particular memory address request hits and/or tries to access one or more entries in a locked set. Devices, systems, methods, and computer readable media are provided.