Method and system for template pattern optimization for DSA patterning using graphoepitaxy
US9558310B2 · kind B2 · utility
1Cited by
7References
9Claims
0Family size
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Key dates
| Filing date | May 28, 2015 |
| Grant date | Jan 31, 2017 |
| Priority date | — |
| Expiry date | Jul 3, 2035 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P90/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for design template pattern optimization, comprises receiving a design for a fin field effect transistor (FinFET) device, wherein the design includes a configuration of fins, creating a design template pattern for the design for use in connection with directed self-assembly (DSA) patterning using graphoepitaxy, and optimizing the design template pattern to minimize pattern density gradients, wherein the design template pattern includes a plurality of guiding lines for guiding a block-copolymer deposited during the DSA patterning and the optimizing comprises altering the guiding lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.