Dimension calculation method for a semiconductor device
US9558565B2 · kind B2 · utility
3Cited by
1References
20Claims
0Family size
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Key dates
| Filing date | Feb 7, 2014 |
| Grant date | Jan 31, 2017 |
| Priority date | — |
| Expiry date | Jan 10, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T2207/30148
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An automatic calculation method for thickness calculation of a deposition layer in a Fin-type field-effect transistor (FinFET) is disclosed through mapping edge lines onto an Excel spreadsheet. The similar method is also applied to the thickness calculation of superlattice or multiple quantum well for a light emitting diode (LED). The edge lines are obtained and transformed from an electronic image taken by Transmission Electron Microscopy (TEM), Focus Ion Beam (FIB), Atomic Force Microscopy (AFM), or X-Ray Diffraction (XRD) of the device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.