SRAM multi-cell operations
US9558812B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 5, 2016 |
| Grant date | Jan 31, 2017 |
| Priority date | — |
| Expiry date | May 5, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-memory cell operator includes a non-destructive memory array, an activation unit and a multiple column decoder. The non-destructive memory array has first and second bit lines per column. The activation unit activates at least two cells in a column of the memory array at the same time thereby to generate multiple Boolean function outputs of the data and of complementary data of the at least two cells on the first bit line and different multiple Boolean function outputs of the data and of the complementary data on the second bit line. The multiple column decoder at least activates the first and second bit lines of multiple selected columns for reading or writing. The multiple column decoder also includes a write unit to write the output of the first bit line, the second bit line or both bit lines of the selected columns into the memory array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.