Nonvolatile memory device and an erasing method thereof
US9558834B2 · kind B2 · utility
4Cited by
7References
20Claims
0Family size
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Key dates
| Filing date | Oct 20, 2015 |
| Grant date | Jan 31, 2017 |
| Priority date | — |
| Expiry date | Oct 20, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/32
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An erase method of a nonvolatile memory device includes applying an erase voltage to a substrate; sensing a temperature of a memory cell array; setting a delay time based on the temperature of the memory cell array, wherein the delay time starts in response to the erase voltage being applied to the substrate; applying a ground voltage to a ground selection line connected to a ground selection transistor during the delay time; and increasing a voltage of the ground selection line after the delay time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.