Compact high speed sense amplifier for non-volatile memory with reduced layout area and power consumption
US9558836B2 · kind B2 · utility
9Cited by
34References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Sep 14, 2015 |
| Grant date | Jan 31, 2017 |
| Priority date | — |
| Expiry date | Sep 14, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A compact and versatile high speed sense amplifier suitable for use in non-volatile memory circuits is presented. The sense amp circuit is connected to first and second supply levels, a first level used for setting a program inhibit level on bit lines and a second level used for pre-charging bit lines for sensing operation. Outside of a data latch, the sense amp can employ only NMOS transistors. The arrangement of the circuit also allows for the discharging the bit line at the same time as transfers the sensing result out to other latches.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.