Method for manufacturing a substrate provided with different active areas and with planar and three-dimensional transistors
US9558957B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 15, 2013 |
| Grant date | Jan 31, 2017 |
| Priority date | — |
| Expiry date | May 15, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A substrate is successively provided with a support (7), an electrically insulating layer (8), and a semi-conductor material layer (2). A first protective mask (1) completely covers a second area (B) of the semi-conductor material layer and leaves a first area (A) of the semi-conductor material layer uncovered. A second etching mask (3) partially covers the first area (A) and at least partially covers the second area (B), so as to define and separate a first area and a second area. Lateral spacers are formed on the lateral surfaces of the second etching mask (3) so as to form a third etching mask. The semi-conductor material layer (2) is etched by means of the third etching mask so as to form a pattern made from semi-conductor material in the first area (A), the first etching mask (3) protecting the second area (B).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.