Chip package and method for forming the same
US9559001B2 · kind B2 · utility
3Cited by
15References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 9, 2011 |
| Grant date | Jan 31, 2017 |
| Priority date | — |
| Expiry date | Jun 6, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1461
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
According to an embodiment of the invention, a chip package is provided, which includes: a substrate having an upper surface and a lower surface; a hole extending from the upper surface toward the lower surface; an insulating layer located overlying a sidewall of the hole; and a material layer located overlying the sidewall of the hole, wherein the material layer is separated from the upper surface of the substrate by a distance and a thickness of the material layer decreases along a direction toward the lower surface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.