Wafer back-side polishing system and method for integrated circuit device manufacturing processes
US9559021B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 4, 2016 |
| Grant date | Jan 31, 2017 |
| Priority date | — |
| Expiry date | Mar 4, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02043
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A wafer polishing process includes polishing a central area on the back side of a wafer, polishing a peripheral area on the back side of the wafer, buffing the central area, and buffing the peripheral area. The process can significantly reduce scratch-related wafer breakage, can correct focus spots on wafers, and can replace cleaning processes that use chemical etchants. Polishing and buffing can include polishing and buffing the bevel region. Further improvements include polishing with abrasive pads having a soft backing, polishing or buffing with pads having relatively soft abrasive particles, polishing or buffing with abrasive pads made from abrasive particles that have been sorted and selected for regularity of shape, irrigating the surface being polished or buffed with an aqueous solution that includes a friction-reducing agent, and buffing with abrasive pads having 20k or finer grit or non-abrasive pads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.