Package with solder regions aligned to recesses
US9559044B2 · kind B2 · utility
4Cited by
3References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 25, 2013 |
| Grant date | Jan 31, 2017 |
| Priority date | — |
| Expiry date | Oct 8, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method includes forming a passivation layer over a portion of a metal pad, forming a polymer layer over the passivation layer, and exposing the polymer layer using a photolithography mask. The photolithography mask has an opaque portion, a transparent portion, and a partial transparent portion. The exposed polymer layer is developed to form an opening, wherein the metal pad is exposed through the opening. A Post-Passivation Interconnect (PPI) is formed over the polymer layer, wherein the PPI includes a portion extending into the opening to connect to the metal pad.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.