Semiconductor stack packages
US9559079B2 · kind B2 · utility
2Cited by
0References
14Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 4, 2015 |
| Grant date | Jan 31, 2017 |
| Priority date | — |
| Expiry date | Mar 4, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor stack package includes a printed circuit board (PCB), a first semiconductor chip, and a second semiconductor chip. The first and second semiconductor chips are disposed side-by-side on a first surface of the PCB to be spaced apart from each other. Each of the first and second semiconductor chips includes a command/address (CA) chip pad and a data input/output (DQ) chip pad. The CA chip pad of the first semiconductor chip is electrically coupled to the CA chip pad of the second semiconductor chip through a CA bonding wire.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.