Independent 3D stacking
US9559081B1 · kind B1 · utility
221Cited by
2References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 6, 2015 |
| Grant date | Jan 31, 2017 |
| Priority date | — |
| Expiry date | Nov 6, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/186
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Packages and 3D die stacking processes are described. In an embodiment, a package includes a second level die hybrid bonded to a first package level including a first level die encapsulated in an oxide layer, and a plurality of through oxide vias (TOVs) extending through the oxide layer. In an embodiment, the TOVs and the first level die have a height of about 20 microns or less.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.