Patent · US Active

Processor hiding its power-up latency with activation of a root port and quickly sending a downstream cycle

US9563256B2 · kind B2 · utility

0Cited by

3References

24Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Sun Zheng E · Balik Pulau, MY
Ting Lok Song · Bayan Lepas, MY
Poh Thiam Teoh · Bandar Baru Sungai Buloh, MY
Jennifer Chin · Bayan Lepas, MY
Say Cheong Gan · Melaka City, MY
Sujea Lim · Bintangor, MY
Su Wei Lim · Klang, MY

Key dates

Filing date	Jan 4, 2013
Grant date	Feb 7, 2017
Priority date	—
Expiry date	Dec 14, 2033

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY02D30/50
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Particular embodiments described herein can offer a method that includes powering down a root port; initiating a first downstream cycle by a central processing unit (CPU) to the root port; identifying a power up activity for the CPU; and triggering an exit flow for a power state in conjunction with sending a second downstream cycle to the root port. In more particular embodiments, the triggering of the exit flow for the power state and the sending of the second downstream cycle to the root port occurs in a substantially parallel fashion. In addition, a prewake indicator can be sent to the root port to trigger the exit flow before the CPU is powered up and the second downstream cycle is sent.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.