Deep-sleep wake up for a memory device
US9564180B1 · kind B1 · utility
10Cited by
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20Claims
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Assignee
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Key dates
| Filing date | Jun 24, 2016 |
| Grant date | Feb 7, 2017 |
| Priority date | — |
| Expiry date | Jun 24, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/148
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device comprises memory banks, power gates, and bank wake-up circuits. Each of the memory banks has a core voltage supply. The power gates are coupled to the memory banks for charging the core voltage supplies and have a plurality of powering modes. The bank wake-up circuits are coupled to the power gates for selecting one of the plurality of power modes for charging the memory banks during a wake-up mode. The bank wake-up circuits sense the core voltage supplies during the wake-up mode. The bank wake-up circuits serially charge the memory banks as a function of the sensed core voltage supplies of the memory banks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.