Methods of fabricating a semiconductor device
US9564325B2 · kind B2 · utility
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10References
16Claims
0Family size
Assignee
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Key dates
| Filing date | Jul 10, 2014 |
| Grant date | Feb 7, 2017 |
| Priority date | — |
| Expiry date | Jan 23, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a semiconductor device is provided. In the method, a first hard mask layer is formed on a stepped structure. The first hard mask layer has a level top surface and thickness sufficient to etch the structure. A second hard mask pattern is formed on the first hard mask layer. The first hard mask layer is etched using the second hard mask pattern. Size dispersion of the patterns may be reduced by the first hard mask layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.