Apparatus and method for rounded ONO formation in a flash memory device
US9564331B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 2, 2012 |
| Grant date | Feb 7, 2017 |
| Priority date | — |
| Expiry date | Aug 9, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/69
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for continuously rounded charge trapping layer formation in a flash memory device. The memory device includes a semiconductor layer, including a source/drain region. An isolation region is disposed adjacent to the source/drain region. A first insulator is disposed above the source/drain region. A charge trapping layer is disposed within the first insulator, wherein the charge trapping layer comprises a bulk portion and a first tip and a second tip on either side of said bulk portion, wherein said charge trapping layer extends beyond the width of the source/drain region. A second insulator is disposed above the charge trapping layer. A polysilicon gate structure is disposed above the second insulator, wherein a width of said control gate is wider than the width of said source/drain region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.