Marker pattern for enhanced failure analysis resolution
US9564380B2 · kind B2 · utility
1Cited by
1References
23Claims
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Key dates
| Filing date | Aug 26, 2014 |
| Grant date | Feb 7, 2017 |
| Priority date | — |
| Expiry date | Dec 7, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A marker pattern for enhancing resolution of a defect location along an axis in semiconductor defect analysis, and in particular, a marker pattern providing greater resolution in locating bit line defects using thermal laser stimulation methods such as OBIRCH. In an example, the marker pattern may consist of large markers, each having a set of associated small markers. Each of the small markers may be offset along an axis from each other. By identifying the small marker and its associated large marker which align with the defect, the bit line containing the defect may be more easily identified.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.