Semiconductor package and method of manufacturing the same
US9564411B2 · kind B2 · utility
3Cited by
1References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 28, 2012 |
| Grant date | Feb 7, 2017 |
| Priority date | — |
| Expiry date | Dec 28, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed herein is a semiconductor package having a fan-out structure in which a semiconductor chip is buried by an encapsulation member and an external connection member is disposed below the buried semiconductor chip. The semiconductor package includes an embedded rewiring pattern layer, an upper semiconductor chip disposed above the embedded rewiring pattern layer, an upper encapsulation member encapsulating the upper semiconductor chip, a lower semiconductor chip disposed below the embedded rewiring pattern layer, and a lower encapsulation member encapsulating the lower semiconductor chip to prevent exposure thereof.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.