Multiple gate field-effect transistors having oxygen-scavenged gate stack
US9564489B2 · kind B2 · utility
260Cited by
11References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 29, 2015 |
| Grant date | Feb 7, 2017 |
| Priority date | — |
| Expiry date | Jun 29, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method includes forming a silicon cap layer on a semiconductor fin, forming an interfacial layer over the silicon cap layer, forming a high-k gate dielectric over the interfacial layer, and forming a scavenging metal layer over the high-k gate dielectric. An anneal is then performed on the silicon cap layer, the interfacial layer, the high-k gate dielectric, and the scavenging metal layer. A filling metal is deposited over the high-k gate dielectric.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.