Instruction and logic for accelerated compressed data decoding
US9564917B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 18, 2015 |
| Grant date | Feb 7, 2017 |
| Priority date | — |
| Expiry date | Dec 18, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M7/6005
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A processor includes an execution unit to decode compressed data. The execution unit includes a code information array, a matching logic unit, a code value generator, and a decoder. The code information array includes a pre-computed code length counter and a pre-computed last code. The matching logic unit includes logic using the code information array to match a segment of a payload of the compressed data with a matching code length and a matching code index. The code value generator includes logic to translate the matching code index into a code value. The decoder includes logic to generate decompressed data from the code value and the matching code length.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.