Recovery of multi-page failures in non-volatile memory system
US9569306B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 18, 2015 |
| Grant date | Feb 14, 2017 |
| Priority date | — |
| Expiry date | Dec 18, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/262
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data storage system includes a controller and a non-volatile memory array having a plurality of blocks each including a plurality of physical pages. The controller maintains a logical-to-physical translation (LPT) data structure that maps logical addresses to physical addresses and implements a first data protection scheme that stripes write data over the plurality of physical blocks. In response to a read request requesting data from a target page stripe, the controller detecting errors in multiple physical pages of the target page stripe. In responsive to detecting errors in multiple physical pages of the target page stripe, the controller scans the LPT data structure to identify a set of logical addresses mapped to the target page stripe and triggers recovery of the target page stripe by a higher level controller that implements a second data protection scheme, wherein triggering recovery includes transmitting the set of logical addresses to the higher level controller.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.