Automatic pipelining of NoC channels to meet timing and/or performance
US9569579B1 · kind B1 · utility
23Cited by
30References
18Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 1, 2015 |
| Grant date | Feb 14, 2017 |
| Priority date | — |
| Expiry date | Jul 23, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods for automatically generating a Network on Chip (NoC) interconnect architecture with pipeline stages are described. The present disclosure includes example implementations directed to automatically determining the number and placement of pipeline stages for each channel in the NoC. Example implementations may also adjust the buffer at one or more routers based on the pipeline stages and configure throughput for virtual channels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.