Projection patterning with exposure mask
US9570301B2 · kind B2 · utility
3Cited by
2References
20Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | May 29, 2014 |
| Grant date | Feb 14, 2017 |
| Priority date | — |
| Expiry date | May 29, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31111
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for fabricating an integrated circuit is provided. The process includes providing a substrate and forming a hard mask on the substrate. The hard mask may be formed by atomic-layer deposition (ALD) or molecular-layer deposition (MLD). The process also includes disposing an exposure mask over the hard mask and exposing the exposure mask to a patterning particle to pattern a gap in the hard mask. The patterning particle may be, for example, a photon or a charged particle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.